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Base pay range

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Our Edinburgh based client is dedicated to providing cutting-edge network monitoring solutions.

About the Role

Reporting to the R&D Project Manager, candidates will be responsible for the architecture, design and verification of FPGA sub-systems within our client's flagship network monitoring products. The role is multi-disciplinary and includes development of FPGA IP Cores, full FPGA System-on-Chip RTL designs and verification testbenches.

Responsibilities

• Architecture, design and verification of FPGA sub-systems.
• Development of FPGA IP Cores.
• Full FPGA System-on-Chip RTL designs.
• Mentoring of less experienced colleagues (for senior roles).

Beneficial Skills to have

• Experience of designing FPGA IP cores or sub-systems.
• Designing FPGA architectures from a technical specification.
• Design with AMD/Intel FPGA and CPLD devices.
• Implementing high speed, multi-frequency clocking architectures.
• Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets.
• Designing for high-speed optical interfaces.
• Designing for high-speed SERDES interfaces (up to 28G/56G).

Seniority level

Mid-Senior level

Employment type

Full-time

Industries

IT Services and IT Consulting

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