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ARM’s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate.

This position offers an excellent opportunity for an experienced and highly motivated design engineer to join the hardworking System IP team!

This is a fast-paced technical role employing the latest hardware design methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems!

The Interconnect team develops the Arm Corelink Interconnect IP family. Our Interconnects and NoCs are designed for intelligent connected systems across a wide range of applications including mobile, IoT, networking infrastructure, automotive, etc. The highly scalable IP is optimized for AMBA-compliant SoC connectivity and can be customized for multiple performance points.

Responsibilities:

• Analyse proposed specifications to understand implementation challenges and opportunities, working with architects to improve and refine ideas.
• Plan, track, and coordinate tasks for yourself and your team.
• Collaborate with modeling, verification, performance analysis, and back-end implementation colleagues to ensure your design meets all functional and performance requirements.
• Improve design methodology to meet evolving needs.

You will be responsible for developing one or more functional blocks of the IP. You should possess an in-depth understanding of all aspects of the product’s successful delivery, including low-power design techniques, awareness of the impact of design decisions on system performance, the ability to produce area-efficient designs, and verification techniques to ensure high-quality, innovative designs.

Required Skills and Experience:

• Proven track record of delivering high-quality, low-power, high-performance micro-architecture and RTL design using SystemVerilog, Verilog, or VHDL within reasonable timescales.
• Ability to make high-level design trade-offs and clearly articulate the rationale behind those choices.
• Knowledge of ASIC (or FPGA) design methodology, IP signoff methods, and understanding of timing, area, and complexity trade-offs for complex data path designs.

'Nice To Have' Skills and Experience:

• Team leadership and mentoring experience.
• Knowledge of memory system interconnect protocols (AMBA ACE-Lite or AXI).
• Solid understanding of SystemVerilog Assertions (SVA) and formal verification.
• Experience with scripting languages such as Perl, Tcl, Python.
• Experience working on Functional Safety product development for the Automotive market, applying standards like ISO 26262 and IEC 61508.

In return -

You will get to utilize your engineering skills to build support for the technologies and influence millions of devices for years to come!

Accommodations at Arm

At Arm, we want our people to Do Great Things. If you need support or an accommodation during the recruitment process, please email us. By sending your request, you consent to its use by Arm to arrange appropriate accommodations. All requests are confidential. Examples include breaks between interviews, documents read aloud, or office accessibility. Please contact us for support during the recruitment process.

Hybrid Working at Arm

Our hybrid approach offers flexibility, allowing teams to determine their own working patterns based on their needs. Details will be shared upon application. Some limitations may apply due to local legal, regulatory, or other considerations. Please contact us to learn more about potential arrangements.