Senior Engineer - Silicon Physical Design (Italy based)

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About Us

Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just three years, we have raised a total of $120 million and have built a world-class team of 180+ employees (including 55+ PhDs with more than 40,000 citations), both remotely from 11 different countries and with offices in Belgium, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.

We have also launched our Metis AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.

Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

Are you up for the challenge?

Position Overview

As a Senior Silicon Physical Design Engineer at Axelera AI, you will play a crucial role in developing cutting-edge multi-core in-memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR signoff, and formal verification. You will collaborate closely with architecture and RTL teams to ensure successful project execution.

Key Responsibilities:

• Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.
• Ensure timing closure, constraint generation, and optimization.
• Execute clock tree synthesis (CTS) and clock-building techniques.
• Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
• Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• Develop automation scripts in Python, Tcl, or Perl.
• Debug and solve technical challenges related to physical design.
• Collaborate with architecture, RTL, and verification teams.
  
  

• 10+ years of experience in Physical Design (RTL to GDS).
• Strong communication and teamwork skills.
• Expertise in synthesis, timing analysis, and timing closure.
• Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre).
• Proficiency in clocking techniques and CTS.
• Experience in IP integration across various domains.
• Strong scripting skills (Python, Tcl, or Perl).
• Proven problem-solving and debugging capabilities.
• Fluent in English (spoken and written). Italian not required.
  
  

• Experience in top-level integration and I/O ring design.
• Knowledge of chip-package-board co-simulation and packaging.
• Ability to influence design methodologies and tool flows.
• Experience working with EDA vendors to resolve tool issues.
• Understanding of semiconductor device physics and multi-domain design.
  
  

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Semiconductor Manufacturing

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